1. Field of the Invention
The present invention relates to a DMA transfer device in which a single bus master device executes two kinds of DMA transfers.
2. Description of the Prior Art
In accordance with recent improvement of the throughput of a personal computer, a demand for performing by means of software a process which is conventionally performed by means of hardware is increasing. For example, there is a case where an encoded stream is fetched into a personal computer and then processed by means of software, and a stream produced as a result of the process is supplied to a device such as a video decoder to be output as an image or sound. FIG. 7 shows a configuration example of the prior art. An encoded first stream which is input through stream inputting means 701 is stored into first stream storing means 702. In response to a transfer request from a processing unit 704, first DMA transfer executing means 703 then executes a DMA transfer of the first stream stored in the first stream storing means 702 to a main storage unit 705. The processing unit 704 reads out the first stream from the main storage unit 705, performs software decoding on the first stream to produce a second stream, and stores the second stream into the main storage unit 705. In response to a transfer request from the processing unit 704, thereafter, second DMA transfer executing means 707 executes a DMA transfer of the second stream stored in the main storage unit 705 to second stream storing means 706.
In the prior art, a bus master device (corresponding to the first DMA transfer executing means 703 and the second DMA transfer executing means 707) which is employed in a DMA transfer is used in both the transfer from the first stream storing means 702 to the main storage unit 705, and that from the main storage unit 705 to the second stream storing means 706.
In the case where the amount of data requested in the first DMA transfer is larger than that of data accumulated in the first stream storing means 702, the bus master device cannot start the first DMA transfer until data of an amount which is equal to the requested data amount in the DMA transfer are accumulated in the first stream storing means 702. Similarly, in the case where the amount of data requested in the second DMA transfer is larger than the free capacity of the second stream storing means 706, the bus master device cannot start the second DMA transfer until a free capacity which is equal to the requested data amount in the DMA transfer is ensured in the second stream storing means 706.
As a result, in the case where, when the processing unit 704 requests the first DMA transfer after the processing unit requests the second DMA transfer, the free capacity is not sufficient for starting the transfer to the second stream storing means 706, for example, the bus master device must wait to perform the first DMA transfer until the second DMA transfer is ended. In the first stream storing means 702, therefore, an overflow occurs in the first stream from the stream inputting means.
Similarly, in the case where, when the processing unit 704 requests the second DMA transfer after the processing unit requests the first DMA transfer, the data amount is not sufficient for starting the transfer to the first stream storing means 702, the bus master device must wait to perform the second DMA transfer until the first DMA transfer is ended. Therefore, an underflow occurs in the second stream storing means 706.
In view of the problems of a DMA transfer method of the prior art, it is an object of the invention to provide a DMA transfer device in which an overflow or an underflow in such first and second stream storing means hardly ever occurs.
One aspect of the present invention is a DMA transfer device comprising:
stream inputting means for receiving an encoded first stream;
first stream storing means for storing the first stream;
a main storage unit which stores the stream of said first stream storing means;
first DMA transfer executing means for executing a first DMA transfer from said first stream storing means to said main storage unit;
first DMA transfer controlling means for controlling said first DMA transfer executing means on the basis of an amount of data which are stored in said first stream storing means or a free capacity;
a processing unit which produces a second stream from the first stream that is read out from said main storage unit, and which writes the second stream into said main storage unit;
second stream storing means for storing the second stream of said main storage unit;
second DMA transfer executing means for executing a second DMA transfer from said main storage unit to said second stream storing means; and
second DMA transfer controlling means for controlling said second DMA transfer executing means on the basis of an amount of data which are stored in said second stream storing means or a free capacity.
Another aspect of the present invention is a DMA transfer device wherein, when the data amount D1 of said first stream storing means is equal to or larger than a data amount D1req which is requested by said processing unit, said first DMA transfer controlling means issues a first DMA transfer start command to said first DMA transfer executing means, and said first DMA transfer executing means executes the first DMA transfer from said first stream storing means to said main storage unit.
Still another aspect of the present invention is a DMA transfer device wherein, when the free capacity E2 of said second stream storing means is equal to or larger than a data amount D2req which is requested by said processing unit, said second DMA transfer controlling means issues a second DMA transfer start command to said second DMA transfer executing means, and said second DMA transfer executing means executes a DMA transfer of the second stream stored in the main storage unit to said second stream storing means.
Yet another aspect of the present invention is a DMA transfer device wherein said DMA transfer device further comprises DMA transfer priority judging means for judging priorities of the first DMA transfer and the second DMA transfer, and
in accordance with a result of the judgement, said DMA transfer priority judging means controls said first DMA transfer controlling means and said second DMA transfer controlling means.
The 5th invention of the present invention is a DMA transfer device, wherein the encoded stream conforms to the MPEG standard, said first and second stream storing means are FIFOs, and said first and second DMA transfer executing means are configured by a bus master device.
A further invention of the present invention is a DMA transfer device, wherein said FIFOs receive a TS input or a PS input.
A still further aspect of the present invention is a medium carrying a program and/or a data for causing a computer to execute a whole or a part of functions of a whole or a part of the invention said medium being processable by a computer.
A yet further aspect of the present invention is an information aggregation which is a program and/or a data for causing a computer to execute a whole or a part of functions of a whole or a part of the means of the invention.